An information handling system (IHS) may include a processor system that employs multiple processors for processing, handling, communicating or otherwise manipulating information. A multi-core processor is one term that describes a processor system with multiple processors or cores integrated on a common integrated circuit. An IHS or processor system may concurrently support multiple operating systems. Moreover, multiple software program applications may execute within the processor system at the same time. For example, a processor system may execute a program application for virus detection while at the same time executing a program for calculating and sending graphics data to a display. A multi-processing environment is an environment in which multiple programs execute or run concurrently. Multi-processing environments are commonplace in conventional processor architectures.
A typical software program application in a processor system consumes memory addresses and input/output (I/O) resources as a normal process during program execution. Processor systems execute load and store operations that employ memory and/or I/O busses. Processor systems rely on the allocation of bus resources as a critical feature of efficient resource management. Memory load/store requests, also known as read/write requests, require the use of a memory bus for data transfers. An active software application may initiate a memory data transfer request to or from a system memory that resides in the IHS. A conventional processor system may include multiple requestors for memory access. Moreover, more than one program running concurrently with other programs may make a memory load/store request thus initiating a memory load/store or information transfer operation. Multiple processors within the processor system may also make a request for a common I/O bus. Thus, the various functional elements of a processor system must compete for and ultimately share resources of the processor system.
A processor system typically includes a resource manager that manages multiple requests for the memory bus and allocates portions of each resource's bandwidth to each resource requester. The processors or processor elements within the processor system are the resource requesters. The balancing of resource requests with resource availability provides the primary challenge in the design of an effective resource manager. The processor system also includes common I/O interface busses that competing requesters must share. More particularly, the processor system shares the common I/O interface bus among competing operating systems, software applications and processor elements. The resource manager allocates bandwidth to competing I/O interface resource requesters. The I/O interface bus communicates with external devices such as, but not limited to, a neighboring processor system, display, keyboard, mouse, media drive, and other devices.
A conventional software architectural hierarchy for a processor system may include a hypervisor, namely a layer of software that controls access of the operating system(s) to processor resources, memory resources, and I/O resources. The hypervisor enables multiple software applications and operating systems to execute in the processor system or IHS without debilitating conflict. The hypervisor controls the resource manager and limits the amount of memory and I/O bus bandwidth the resource manager allows per program application, thus providing an environment for multiple program applications to effectively co-exist cooperatively within the processor system. The resource manager controls the memory bandwidth and I/O bus bandwidth by limiting or restricting the use of the memory and I/O busses. Without such a resource manager, one application could consume I/O resources in an unrestricted manner, thus not allowing another application to receive sufficient bus bandwidth to complete application tasks within a reasonable timeframe. Poor resource management of the memory bus or I/O bus may create undesired conditions such as continuous re-try or program halt. More particularly, poor bus resource management may cause the processor system to inefficiently consume limited bus bandwidth resources.
Processor systems wherein a processor or single integrated circuit includes multiple cores or processor elements as well as memory and I/O controllers are now commonplace. Such a processor system is sometimes referred to as a multi-core processor or system-on-a-chip (SoC). Such a processor system may include one or more hardware units (HUs) that are capable of requesting access to memory and I/O resources. HUs may include a general processor core or cores, a specific processor core or cores, and I/O controllers that may initiate requests on behalf of I/O devices. A resource manager in such a multi-core processor may allocate portions of memory and I/O bandwidth to resource allocation groups (RAGs) of the hardware units in the processor system. Unfortunately, this allocation is typically relatively coarse. For example, it does not address differing resource needs among multiple operating systems or program applications running on a single hardware unit. Such a coarse allocation of resources may cause operational problems in the processor system or IHS. For example, with such a coarse allocation of resources, a high bandwidth application such as a virus scan may effectively starve execution of a user-interactive application such as a graphical user interface. This may cause a detrimental effect on the user experience.
What is needed is a method and apparatus that addresses the problems faced by resource managers in processor systems such as described above.